Receiving circuits for receiving parallel data are known in the art.
In the case of parallel data, a difference (skew) can occur in the arrival times of data at the receiving circuit due to such factors as variations in the characteristics of the signal lines used to carry the data or the circuit elements constituting the transmitting circuit used to transmit the data.
When receiving such parallel data, it is preferable to use a clock that provides timing with which all of the data can be received in synchronized fashion.
Therefore, the receiving circuit for receiving the parallel data adjusts the phase of the clock so as to be able to receive the data in synchronized fashion, and receives the parallel data by using the thus adjusted clock.
FIG. 1 is a diagram illustrating a digital camera incorporating a prior art receiving circuit.
The digital camera 101 includes a memory card 120 which stores image data and a receiving circuit 110 which receives parallel data output from the memory card 120. The digital camera 101 also includes a main control unit 102 which controls the receiving circuit 110 and a main storage unit 103 which stores the parallel data received by the receiving circuit 110. The digital camera 101 further includes an imaging unit not depicted and a transmitting circuit which transmits captured image data to the memory card 120.
The receiving circuit 110, under control of the main control unit 102, receives the image data output from the memory card 120 and supplies the received image data to the main storage unit 103.
As depicted in FIG. 2, the memory card 120 simultaneously outputs 8-bit parallel data for transmission to the receiving circuit 110 via eight data lines D0 to D7 in synchronism with a reference clock supplied from the receiving circuit 110.
When the data transmitted via the data lines D0 to D7 are received at the receiving circuit 110, skew is present between the data N−1, N transmitted via the data line D0 and the data N−1, N transmitted via the data line D7.
Then, in order to receive the transmitted parallel data in synchronized fashion, the receiving circuit 110, using test parallel data, determines a receive clock that provides timing with which the data can be received, and starts to receive the image data by using the thus determined receive clock. The receive clock is determined so that the timing falls within a receivable period during which all of the data can be received in synchronized fashion. After determining the receive clock by using the test parallel data, the receiving circuit 110 starts to receive the image data.
Next, a description will be given of how the receiving circuit 110 determines the receive clock.
The receiving circuit 110 includes a PLL 111 as a phase-locked loop circuit which generates the reference clock. The PLL 111 supplies the generated reference clock to a DLL 112 as well as to the memory card 120.
The DLL 112 is a delay-locked loop circuit which takes as an input the reference clock generated by the PLL 111 and outputs delayed clocks delayed in phase with respect to the reference clock. As illustrated in FIG. 3, the DLL 112 generates delayed clocks, one having the same phase as the reference clock (delayed phase 0) and the others having delayed phases respectively delayed by 1T/8 to 7T/8 with respect to the phase of the reference clock, where T is one clock period of the reference clock. The eight delayed clocks are shifted in phase by T/8 relative to each other.
The DLL 112 supplies the generated delayed clocks to a storage unit 113. The storage unit 113 includes eight flip-flops (FF0 to FF7). Each of the flip-flops FF0 to FF7 is connected to a corresponding one of the eight data lines D0 to D7 and, in synchronism with the delayed clock supplied from the DLL 112, receives and holds one-bit data out of the 8-bit parallel data transmitted from the memory card 120.
A DLL control unit 117, under control of the main control unit 102, controls the delayed phase of the delayed clock that the DLL 112 generates. The DLL 112 generates the delayed clock having the delayed phase specified by the DLL control unit 117.
Further, the DLL control unit 117 directs the memory card 120 to transmit test parallel data and image data. Data having a cyclic redundancy check code, for example, can be used as the test parallel data.
When an instruction requesting transmission of test parallel data is received from the DLL control unit 117, the memory card 120 transmits the test parallel data to the receiving circuit 110 via the eight data lines in synchronism with the reference clock.
The receiving circuit 110 receives the test parallel data by using each of the eight delayed clocks having different delayed phases, and determines a phase range containing any delayed phase with which the test parallel data can be received correctly. Then, from the thus determined phase range, the receiving circuit 110 determines the phase of the receive clock to be used for reception of the parallel data.
First, the DLL control unit 117 instructs the DLL 112 to generate the delayed clock whose delayed phase is the same as the phase of the reference clock, and also instructs the memory card 120 to transmit out the test parallel data.
The storage unit 113 receives and holds the test parallel data in synchronism with the delayed clock supplied from the DLL 112. More specifically, each of the flip-flops FF0 to FF7 in the storage unit 113 receives and holds one-bit data in synchronism with the delayed clock, and outputs the thus held data to a judging unit 115.
The judging unit 115 that received the test parallel data from the storage unit 113 checks the data by using a cyclic redundancy check code, judges whether the data has been received correctly or not, and supplies the result of the judgment to the DLL control unit 117.
The DLL control unit 117 that received the result of the judgment then instructs the DLL 112 to generate a delayed clock having a delayed phase delayed by 1T/8 with respect to the phase of the reference clock, and also instructs the memory card 120 to transmit out the test parallel data.
By repeating the above process, the receiving circuit 110 determines the phase range containing any delayed phase with which the test parallel data can be received correctly.